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| DM74174 Hex/Quad D-Type Flip-Flop with Clear September 1986 Revised February 2000 DM74174 Hex/Quad D-Type Flip-Flop with Clear General Description These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input. Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. Features s Contains six flip-flops with single-rail outputs s Buffered clock and direct clear inputs s Individual data input to each flip-flop s Applications include: Buffer/storage registers Shift registers Pattern generators s Typical clock frequency 40 MHz s Typical power dissipation per flip-flop 38 mW Ordering Code: Order Number DM74174 Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table (Each Flip-Flop) Inputs Clear L H H H Clock X L D X H L X Outputs Q L H L Q0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established. (c) 2000 Fairchild Semiconductor Corporation DS006557 www.fairchildsemi.com DM74174 Logic Diagram www.fairchildsemi.com 2 DM74174 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK tW Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Pulse Width (Note 2) tSU tH tREL TA Clock LOW Clock HIGH Clear Data Setup Time (Note 2) Data Hold Time (Note 2) Clear Release Time (Note 2) Free Air Operating Temperature 0 25 10 20 20 0 30 0 70 ns ns ns C ns Min 4.75 2 0.8 -0.8 16 30 Nom 5 Max 5.25 Units V V V mA mA MHz Note 2: TA = 25C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = -12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max, VI = 2.4V VCC = Max, VI = 0.4V VCC = Max (Note 4) VCC = Max (Note 5) -18 45 2.4 0.4 1 40 -1.6 -57 65 Min Typ (Note 3) Max -1.5 Units V V V mA A mA mA mA Note 3: All typicals are at VCC = 5V, TA = 25C. Note 4: Not more than one output should be shorted at a time. Note 5: With all outputs open and all DATA and CLEAR inputs at 4.5V, ICC is measured after a momentary ground, then 4.5V applied to the CLOCK input. Switching Characteristics at VCC = 5V and TA = 25C Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output Clock to Any Q Clock to Any Q Clear to Any Q From (Input) To (Output) RL = 400, CL = 15 pF Min 30 25 25 40 Max MHz ns ns ns Units 3 www.fairchildsemi.com DM74174 Hex/Quad D-Type Flip-Flop with Clear Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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